CSE517: Hardware Description Language

Tuesdays and Thursday 1.40 pm – 2.55 pm

Fall 2003.

 

Course Description

Pre-requisites

Textbook

Instructor

Office Hours

Teaching Assistant

Evaluation Policy

Grading Policy

Announcements

Resources

Assignments

Tool Update

 

Lecture Slides

 

 

     ANNOUNCEMENT FOR CSE 422 STUDENTS TAKING THE CLASS IN FALL 2004:

     QUESTION 6 OF ASSIGNMENT 2 (BCD AND RESOLVED SIGNALS) NEED NOT BE TURNED IN

Course Description (Syllabus: ps file , pdf file)

The course will cover the standard IEEE VHDL-2003 hardware description language. The course will begin with the motivation for using hardware description languages. It will give a brief overview of hardware design and introduce the various the levels of design abstraction from behavioral to gate level. The course will then cover various constructs that are provided by VHDL for modeling and simulation of digital systems at different levels of design abstraction.

Pre-requisites

q       Digital design fundamentals

q       High-level programming language

Textbook

Dr. Peter Ashenden’s “Designers Guide to VHDL, 2nd Edition”, Morgan Kaufmann Publishers, ISBN 1-55860-674-2.

Instructor

Dr. Karam S. Chatha,

GWC 352,

Department of Computer Science and Engineering,

Arizona State University.

Email: Karam.Chatha@asu.edu

Phone: 480-7277850

Office Hours

Tuesdays and Thursdays from 3.00 pm to 4.00 pm (or by appointment).

Teaching Assistant

Krishnan Srinivasan

Office hours: Monday, Wednesday, 1.00 pm – 2.30 pm

Office location: VLSI lab, University center

Email: ksrini@asu.edu

Evaluation Policy

1.     Class participation – 5 %

2.     Assignments – 20 %

3.     Midterm – 25 %

4.     Project – 25 %

5.     Final exam – 25 %

Grading Policy

1.     Final score >= 90% : A

2.     70% <= Final score < 90% : B

3.     50% <= Final score < 70% : C

4.     Final score < 50 % : F

Announcements

1.     Students who are registered at various campuses (asu main, asu east, asu west) must take their midterm and final exams at their respective sites.

2.     Plagiarism will not be tolerated under any circumstances.

3.     Assignment turn in policy:

a.     Written assignments are to be submitted in the classroom on the due date, OR

b.     In my office by 3.55 pm.

c.     Exceptions will be announced in the classroom or posted on the web page.

d.     Any assignment submitted later than that will be considered as late submissions.

4.     Late submissions will lose 10% of the grade for each delayed day.

5.     Guidelines for programming assignments ( postscript , pdf ).

6.     USERNAMES AND PASSWORDS: Collect them from TA during office hours. Picture ID is required.

7.     MIDTERM date: October 16th, 2003

8.     FINAL date: December 9th, 2003.

9.     Instructions for submission of assignments and problems is given here (ps, pdf)

 

 

Resources

1.     VHDL Language reference manual (LRM).

 

Assignments

1.     Assignment 1 ( ps , pdf ) Date assigned: Thursday, September 11th,03. Submission date: Tuesday, September 23rd, 03

2.     Assignment 2 ( ps , pdf ) Date assigned: Tuesday, September 23rd,03. Submission date: Thursday, October 2nd , 03

3.     Assignment 3 (ps ,  pdf ) Date assigned: Thursday, October 2nd ,03. Submission date: Tuesday, October 14th , 03

4.     Assignment 4 (ps ,  pdf ) Date assigned: Tuesday,  October 21st ,03. Submission date: Thursday, October 30th , 03

5.     Assignment 5 (ps ,  pdf ) Date assigned: Thursday, October 30th,03. Submission date: Thursday, November 13th, 03

6.     Assignment 5 (ps ,  pdf ) Date assigned: Tuesday, November 25th,03. Submission date: Tuesday, December 9th, 03

 

  Project

                   Please find the project description here (ps, pdf)

     Time line

1.     Project Assigned: Tuesday, October 7th, 2003.

2.     Behavioral model preliminary progress report due: October 21st, 2003.

3.     Behavioral model and final report due: November 4th, 2003.

4.     Structural model preliminary progress report due: November 11th, 2003.

5.     Structural model and final report due: December 11th, 2003.

              

Tool Update

·        You will use the Cadence nclaunch VHDL simulator hosted on Sun workstations at University Center 201 (VLSI lab).

·        Short tutorial ( ps , pdf )

 

Lecture Slides

1.     Date: Tuesday, Aug 26, 2003.

Title: Introduction ( html , postscript , pdf )

2.     Date: Thursday, Aug 28, 2003.

Title: VHDL, Introduction ( html ,  postscript , pdf )

3.     Date: Tuesday, Sep 2, 2003.

Title: Simulation and BNF ( html ,  postscript , pdf )

4.     Date:  Thursday, Sep 4, 2003.

Title: Simulation, lexical elements and scalar data types ( html ,  postscript , pdf )

5.     Date: Tuesday, Sep 9, 2003.

Title: Behavior modeling: entity, architecture, process and sequential statements ( html ,  postscript , pdf )

6.     Date: Thursday, Sep 11, 2003.

Title: Behavior modeling: Signal Assignment ( html ,  postscript , pdf )

7.     Date: Tuesday, Sep 16, 2003.

Title: Behavior modeling: Wait statements ( html , postscript , pdf )

8.     Date: Thursday, Sep 18, 2003.

Title: Behavior modeling: Wait statement and Arrays ( html , postscript , pdf )

9.     Date: Tuesday, Sep 23, 2003.

Title: Behavior modeling: Composite Data Types and Modeling Exercise ( html , postscript , pdf )

10. Date: Thursday, Sep 25, 2003.

Title: Behavior modeling: Libraries and Packages ( html , postscript , pdf )

11. Date: Tuesday, Sep 30, 2003.

Title: Behavior modeling: Procedures and Functions ( html , postscript , pdf )

12. Date: Thursday, Oct 2, 2003.

Title: Behavior modeling: Procedures and Functions ( html , postscript , pdf )

13. Date: Tuesday, Oct 7, 2003.

Title: Behavioral modeling: Resolved Signal ( html , postscript , pdf )

14. Date: Thursday, Oct 9, 2003.

Title: aliases and generics ( html , postscript , pdf )

15. Date: Thursday, Oct 14, 2003.

Title: REVIEW  ( html , postscript , pdf )

16. Date: Thursday, Oct 16, 2003.

               ANNOUNCEMENT FOR CSE 422 STUDENTS TAKING THE CLASS IN FALL 2004:

               QUESTION 6 OF ASSIGNMENT 2 (BCD AND RESOLVED SIGNALS) NEED NOT

               BE TURNED IN

 

     Title: MIDTERM, Sample midterm from Fall 2001  ( postscript , pdf ) [ SOLUTIONS: postscript , pdf ]

     Title: MIDTERM, Sample midterm from Fall 2002  (postscript, pdf)

     Title: FINAL, sample final from Fall 2002 (postscript, pdf)

17. Date: Tuesday, Oct 21, 2003.

Title: Behavior modeling: Concurrent Statements ( html , postscript , pdf )

18. Date: Thursday, Oct 23,

19. Date: Tuesday Oct 28, and

20. Date: Thursday Oct 30 2003.

Title: Behavior modeling: File I/O and Textio ( html , postscript , pdf )

21. Date: Tuesday, Nov 4 and 

22. Date: Thursday, Nov 6, 2003.

Title: Components and Configurations ( html , postscript , pdf )

23. Date: Tuesday, Nov 11,

24. Date: Thursday, Nov 13, 2003, and

25. Date: Tuesday, Nov 18, 2000.

Title: Generate Statements ( html , postscript , pdf )

26. Date: Thursday, Nov 20, 2003.

27. Date: Tuesday, Nov 25, 2003.

Title: Guards and Blocks ( html , postscript , pdf )

28. Date: Tuesday, Dec 4, 2003.

Title: Attributes and Groups ( html , postscript , pdf )

29. Date: Thursday, Dec 6, 2003.

Title: Final Review ( html , postscript , pdf )

30. Date: Tuesday, Dec 9, 2003.

Title: FINAL EXAM ( SAMPLE EXAM postscript , pdf )