(Revision 1 31 October 2000)
overview exc_tlbs is actually an entry point in exc_mod that handles TLB Modified exceptions and TLB Invalid Store exceptions and has a small amount of other code not covered in L4.8 and L4.9. TLB load exceptions are handled by a separate routine exc_tlbl which is almost identical except it omits one instruction - so it is also covered in L4.8 and L4.9 . For more on exactly what's in these routines see the source code listing exc.S. TLB refill exceptions are initially handled by the fast TLB miss handler xtlb_refill (L4.1) which is invoked via a separate hardware interrupt vector. The exceptions handled by exc_tlbs and exc_tlbl are defined as follows:
TLB Invalid Load TLB entry exists but v bit off on a load TLB Invalid Store TLB entry exists but v bit off on a store TLB Modified TLB entry exists and v bit on but d bit off on a store
get here after one of the above 3 faults causes general exception handler (geh L4.3) to be invoked, geh jumps (l6) to other_except (L4.6) which uses K_EXC_JMP_TABLE to jump (l60) to the appropriate routine based on exception cause. Causes which are stored in the CAUSE register when exception happens are:
TLB Invalid Load CA_TLBL (2<<2) TLB Invalid Store CA_TLBS (3<<2) TLB Modified CA_MOD (1<<2)
on entry s2 EPC s3 Exception VA s4 CAUSE
| 0 | If an attempt is made to access an unmapped tcb (because the thread was nonexistent), the faulting VA will be negative because tcbs are in mapped virtual memory in one of the CKSEGs (CKSEG3 or CKSSEG) whose leading address bits are 1's - see Figure 2.2. This case is handled on line 51. |
| 1 | t2 ¬ sp |
| 2-27 | Deal with page faults during long IPC - covered later |