(Revision 1 31 October 2000)
overview - handles TLB load, store and modify exceptions (see prologue)
on entry s2 EPC s3 Exception VA s4 CAUSE
| 30-33 | Enable interrupts- need a preemption point to avoid livelocks. TLB faults have higher priority than interrupt exceptions. If user's pager sends an invalid mapping, TLB fault will happen again immediately on return from exception. Timer interrupts will never be serviced and L4 will not be able to regain control of the CPU. |
| 28, 34-37 | Set up a pseudo-exception stack so that the ipc code invoked at line 49 will, when it does a syscall_ret (l52 L5.2), return to the exception return code which will return properly to user code. |
| 29, 38-50 | Set up an IPC register message to the user's pager. Message contains fault address, writable bit (if required), EPC, send and receive descriptors, timeouts, destination and wait-for tids. k_ipc is called just as if the call came directly from geh l23 L4.3. |
| 51-55 | Handles page faults in the TCB array. Invokes routines which allocate a GPT leaf node and insert the physical address of the frame containing the 'invalid TCB' , 49000H , (see figure 3.1). Normal TLB refill handling will validate the mapping. |
| 56 | Return to other_except_ret, the return code for 'other exceptions' of which this is one. |