Solution 4 :

(i) To design a symmetric CMOS inverter :

KP = KN

k'P. (WP/LP) = K'N(WN/LN)

10 .(WP/0.6) = 30. (WN/LN)

WP = 3µ

 

(ii) To verify VM = Vdd/2

VM = [ Vdd + Vt,P + Vt,N Sqrt (1) ] / [ 1 + Sqrt(1) ]

VM = [3.3 - 1 +1] / [1 +1] = 3.3/2 = Vdd/2

Hence proved