FALL  2000

REVISED 11/14/00

EEE425/591 ASU COURSE OUTLINE

SLNs: EEE425 =  68885 ;  EEE591 = 24400     TT 12:15 - 1:30;  SCOB 105
DIGITAL INTEGRATED CIRCUITS AND SYSTEMS
NUMBER OF LECTURE HOURS/SESSIONS: ~30 (75min)

DAYS/TIME/ROOM ON CAMPUS:  TT 12:15 to 1:30 PM(PST) SCOB 105

PREREQUISITES: COURSE(S) IN ELECTRONIC CIRCUITS AND DIGITAL LOGIC

TEXTBOOK: "DIGITAL INTEGRATED CIRCUITS" by DEMASSA, CICCONE, John  Wiley & Sons, 1996

INSTRUCTOR; Thomas A DeMassa
E-MAIL; DeMassa@asu.edu
Web Site; www.eas.asu.edu/~demassa/

COURSE DESCIPTION:  DIGITAL INTEGRATED CIRCUITS WITH EMPHASIS ON CMOS. OPERATION AND DESIGN OF TTL, ECL, NMOS, CMOS AND GaAs DIGITAL LOGIC CIRCUITS. ADDITIONAL TOPICS INCLUDE BiCMOS AND SEMICONDUCTOR MEMORY CIRCUITS.

500 LEVEL MEZZANINE COURSE AVAILABLE FOR GRADUATE CREDIT AT ASU

COURSE OBJECTIVES: TO PROVIDE EXTENSIVE KNOWLEDGE OF THE OPERATION AND DESIGN OF DIGITAL ICs INCLUDING TTL, ECL, NMOS, AND CMOS TECHNOLOGIES WITH EMPHASIS ON CMOS; TO INTRODUCE BiCMOS AND TO PROVIDE AN EXTENSIVE DESCRIPTION OF THE OPERATION AND DESIGN OF GaAs DIGITAL LOGIC FAMILIES; TO PROVIDE COMPUTATIONAL AND SPICE COMPARISONS REGARDING THE VOLTAGE TRANSFER CHARACTERISTIC, FAN-OUT, POWER DISSIPATION AND SPEED OF EACH; TO PROVIDE A DES-CRIPTION OF RANDOM ACCESS MEMORY (RAM) AND READ-ONLY MEMORY(ROM).

COURSE REQUIREMENTS:

HOMEWORK: Homework Assigned but not collected

EXAMINATIONS: 2 MID-TERM EXAMS AND A FINAL EXAM

GRADING:

EEE591: 2 EXAMS (1hr and 15 min)=60%, FINAL EXAM=40%
OR
EEE425: 2 EXAMS=50%, FINAL EXAM=25%, LAB=25%
(SOLUTIONS TO EXAMS WILL BE DISTRIBUTED ASAP) 

 

ASU COURSE OUTLINE BY TOPICAL AREAS AND CHAPTERS

LECTURE 1(TUES 8/22) HOMEWORK PROBLEMS ASSIGNED(HPA):1.1,4,7,10,22,25

PROPERTIES OF DIGITAL CIRCUITS: inverting and noninverting gates, ideal logic elements, voltage transfer characteristic(VTC), logic swing, transition width, noise, fan-in, fan-out, transient characteristics, power dissipation, power-delay product
LECTURE 2 (THUR 8/24) HPA:2.1,5,9,10,16,19; 3.1,2,6,9,11,14
DIODES: PN junction and MN Schottky, modeling, capacitance, SPICE model, diode-resistor logic, level-shifting and clamping diodes
BIPOLAR JUNCTION TRANSISTORS (BJTs): junction isolated and oxide isolated NPNs, multi-emitter, Schottky-clamped, lateral PNP, Ebers-Moll model, Gummel-Poon model, modes of operation, SPICE model, IC resistors and diodes
LECTURE 3 (TUES 8/29) HPA: 4.1,4,8,12,17,23; 5.1,6,11,23,27
INTRODUCTION TO BJT DIGITAL CIRCUITS: analysis, BJT inverter, power dissipation
RESISTOR-TRANSISTOR LOGIC (RTL): inverter and noninverter, NOR gate, NAND gate, fan-out, power dissipation, active pull-up SPICE simulation
LECTURE 4(THUR 8/31) HPA: 6.1,3,7,8,10,12 & 7.1,3,6,10,14,18,21
DIODE TRANSISTOR LOGIC (DTL): inverter, modified DTL, BJT modified, NAND gate, fan-out, power dissipation, SPICE simulation.
TRANSISTOR-TRANSISTOR LOGIC (TTL):inverter, charge removal, NAND gate, totem pole output, VTC, fanout, power dissipation, open collector, low power, high speed, SPICE simulation
LECTURE 5(TUES 9/5) HPA: 8.1,3,6,9,15,20,25; 9.1,5,13,15
SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL): Schottky diodes, Schottky BJTs, STTL inverter, NAND gate, VTC, fan-out, power dissipation, low power LSTTL, SPICE simulation
LECTURE 6 (THUR 9/7) HPA: 10.2,3,16,24
OTHER TTL GATES: AND gates, NOR gates, OR gates, AOI gates, XOR gates, Schmitt inverters and NAND gates

 REVIEW SESSION TUES 9/12 REVIEW of BJT DICs(without ECL)
 

EXAM 1  THURS  (9/14)   AED 60(Architecture and Environmental Design Room 60)
 

EXAM 1 REVIEW TUES 9/19 WILL NOT OCCUR, INSTEAD
FIRST MOS LECTURE ON CHAPTER 16(LECTURE 12)

LECTURE 7 & 8(THUR&TUES 9/21,26) HPA: 11.1,6,8,14,19; 12.1,4,7,10
EMITTER-COUPLED LOGIC (ECL): BJT current switch, VTC, NOR/OR gate, output buffers, MECL I, fan-out, power dissipation, SPICE simulation. TEMPERATURE COMPENSATING ECL: MECL II, bias network, fan-out, power dissipation, SPICE simulation
LECTURE 9&10 (THUR &TUES 9/28,10/3) HPA: 13.1,3,10,14; 14.1,5,8,10;15.2,3,5,6
MORE ECL: MECL III, ECL 10K, ECL100K, power dissipation, SPICE simulation
OTHER ECL GATES: NOR/OR gates, collector dotting, series gating, NAND/AND gates, complex OR-AND gates, XNOR/XOR gates.  ECL REVIEW  and Problem Session
LECTURE 11
THURSDAY 10/5  EXAM 1A
(covering CH1-15   Room AED 60)

Tuesday(10/10) EXAM 1A  REVIEW
 

LECTURE 12(TUES10/10) This lecture given 9/19; HPA:16.2,6,11,12

        MOSFETs: metal gate, silicon gate, N- & P-channel, modes of operation,transconductance
        parameter, threshold voltage, capacitance, SPICE model, CMOS devices, stacked
        MOSFETs

LECTURE 13 (THUR 10/12) HPA:17.2,9,13,20; 18.1,2,3,10 12
RESISTOR LOADED NMOS INVERTERs: operation, graphical determination of VTC, calculation of critical voltages, power dissipation, SPICE simulation

LECTURE 14,15 (TUES&THUR  10/17,19) 19.1,2,3,17; 20.1,2,3,7; 21.1,2,3,11
          SATURATED ENHANCEMENT-ONLY LOADED NMOS INVERTER: same as R-loaded
          LINEAR E-O LOADED NMOS INVERTER: same as R-loaded
          ENHANCEMENT-DEPLETION LOADED NMOS INVERTER: same as R-loaded
          NMOS GATES: NOR, NAND, OR, AND, AOIs, XOR/XNOR, trans gates, Schmitt inverter

LECTURE 16  (TUES 10/24) HPA: 22.2,3,5,9,15,31,38,40,43,50
        NMOS Gates, transmission gates, Schmitt inverter.REVIEW of FETs, REVIEW of NMOS

LECTURE 17,18 (TH, TUES 10/26,31 ) HPA: 23.1,2,3,4; 24.1,2,3,4,7,12,13,21,31,34,35

CMOS INVERTER: operation, power dissipation, graphical determination of VTC, calculation of critical voltages, design of symmetric inverter or minimum size, inverter capacitance, dynamic response, SPICE simulation, latch-up, input clamping
CMOS LOGIC GATES: NAND, NOR, AND, OR, AOI, OAI, XNOR/XOR; BiCMOS
LECTURE 19 (THUR 11/2)  HPA: 25.1,2,4,7,11

        CMOS TRI-STATE LOGIC GATES: high impedance Z-states, contention X-states, tri-state inverters,
        applications, transmission gates

LECTURE 20 (TUES 11/7)  HPA: 26.1,3,8,10,13,15;  27.1,3,5,7

CMOS SCHMITT TRIGGER GATES: inverter, operation and VTC, design, buffered, output, feedback, NAND gate.
CMOS DRIVERS: cascaded inverters driving a load cap, multi-stage inverter driver, tri-state pad drivers, break-before-make circuit;
LECTURE 21(THUR 11/9)HPA:  28.2,4,8,16,19;  30.4,5,9
DYNAMIC CMOS , BiCMOS
LECTURE 22,23  (TUES,THUR 11/14,16) HPA: 34.3,6,7,10; 35.2,5,7,10; 36.2,3,4,6
GaAs METAL SEMICONDUCTOR FETs (MESFETs): N-channel, E-D, E-O, modes of operation, transconductance parameter, threshold voltage, capacitance, SPICE simulation
DIRECT COUPLED NMESFET INVERTER (DCFL): E-O inverter, operation, graphical determination of VTC, calculation of critical voltages, power dissipation, fan-out, SPICE simulation
SCHOTTKY DIODE NMESFET LOGIC (SDFL) INVERTER: E-D inverters,operation, calculation of critical voltages, power dissipation, fan-out, SPICE simulation.
BUFFERED NMESFET LOGIC (BFL) INVERTER: same as SDFL inverter.
LECTURE 24 (TUES 11/21 ) HPA:37.1,2,3,4; 39.1,2,3,9
GaAs LOGIC FAMILY GATES: DCFL NOR, NAND and OR GATES, SDFL NOR and NAND gates, BFL NOR and NAND gates, complex AOI & OIA gates, DCFL XOR, other OR/NOR gates and GaAs problem review.

Thanksgiving Holiday(11/23)

REVIEW SESSION TUES 11/28

EXAM 2  THUR  (11/30)  Room BAC 116
LECTURE 25(TUES 12/5 Last day of classes Fall 2000 )   EXAM 2 REVIEW and REVIEW FOR FINAL

FINAL EXAM      TUESDAY 12/12: 12:20 to 2:10 P.M.(1hr 50min)

(AED 60)
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