SUMMER 2001

EEE425/591 ASU(NTU 740W) COURSE OUTLINE

DIGITAL INTEGRATED CIRCUITS AND SYSTEMS

CLASS MEETS ON CAMPUS in SCOB 105(10 to 11:15 A.M.): 75 minute sessions each Monday through Thursday

PREREQUISITES: COURSE(S) IN ELECTRONIC CIRCUITS AND DIGITAL LOGIC

TEXTBOOK: "DIGITAL INTEGRATED CIRCUITS" by DEMASSA, CICCONE, John Wiley & Sons, 1996

INSTRUCTOR; Thomas A. DeMassa, Professor Emeritus
DeMassa@asu.edu
http://www.eas.asu.edu/~demassa

COURSE DESCIPTION: DIGITAL INTEGRATED CIRCUITS WITH EMPHASIS ON CMOS. OPERATION AND DESIGN OF TTL, ECL, NMOS, CMOS AND GaAs DIGITAL LOGIC CIRCUITS. ADDITIONAL TOPICS INCLUDE BiCMOS AND SEMICONDUCTOR MEMORY CIRCUITS.

500 LEVEL MEZZANINE COURSE AVAILABLE FOR GRADUATE CREDIT AT ASU

COURSE OBJECTIVES: TO PROVIDE EXTENSIVE KNOWLEDGE OF THE OPERATION AND DESIGN OF DIGITAL ICs INCLUDING TTL, ECL, NMOS, AND CMOS TECHNOLOGIES WITH EMPHASIS ON CMOS; TO INTRODUCE BiCMOS AND TO PROVIDE AN EXTENSIVE DESCRIPTION OF THE OPERATION AND DESIGN OF GaAs DIGITAL LOGIC FAMILIES; TO PROVIDE COMPUTATIONAL AND SPICE COMPARISONS REGARDING THE VOLTAGE TRANSFER CHARACTERISTIC, FAN-OUT, POWER DISSIPATION AND SPEED OF EACH; TO PROVIDE A DES-CRIPTION OF RANDOM ACCESS MEMORY (RAM) AND READ-ONLY MEMORY(ROM).

COURSE REQUIREMENTS:

HOMEWORK: Assigned, but not collected
EXAMINATIONS: 3 MID-TERM EXAMS AND A FINAL EXAM
All Exams are in Physical Sciences Bldg PS H153
GRADING:
3 EXAMS (1hr and 15 min) = 60%, FINAL EXAM = 40%
OR 3 EXAMS = 50% FINAL EXAM = 25%, LAB = 25%

COURSE OUTLINE BY TOPICAL AREAS AND CHAPTERS

LECTURE 1(TUES 5/29) HOMEWORK PROBLEMS ASSIGNED(HPA):1.1,4,7,10,22,25

PROPERTIES OF DIGITAL CIRCUITS: inverting and noninverting gates, ideal logic elements, voltage transfer characteristic(VTC), logic swing, transition width, noise, fan-in, fan-out, transient characteristics, power dissipation, power-delay product

LECTURE 2 (WED 5/30) HPA:2.1,5,9,10,16,19; 3.1,2,6,14

DIODES: PN junction and MN Schottky, modeling, capacitance, SPICE model, diode-resistor logic, level-shifting and clamping diodes

BIPOLAR JUNCTION TRANSISTORS (BJTs): junction isolated and oxide isolated NPNs, multi-emitter, Schottky-clamped,lateral PNP,Ebers-Moll model, Gummel-Poon model, modes of operation, SPICE model, IC resistors and diodes

LECTURE 3 (THUR 5/31) HPA: 4.1,4,8,12,17,23; 5.1,6,11,23,27

INTRODUCTION TO BJT DIGITAL CIRCUITS: analysis, BJT inverter,power dissipation

RESISTOR-TRANSISTOR LOGIC (RTL): inverter and noninverter, NOR gate, NAND gate, fan-out, power dissipation, active pull-up SPICE simulation, DCTL and current hogging

LECTURE 4 (MON 6/4) HPA: 6.1,3,7,8,10,12

DIODE TRANSISTOR LOGIC (DTL): inverter, modified DTL, BJT modified, NAND gate, fan-out, power dissipation, SPICE simulation

LECTURE 5 (TUES 6/5) HPA: 7.1,3,6,10,14,18,21, 8.1,3,6,9,15,20,25

TRANSISTOR-TRANSISTOR LOGIC (TTL):inverter, charge removal, NAND gate, totem pole output, VTC, fanout, power dissipation, open collector, low power, high speed, SPICE simulation

LECTURE 6,7( WEDS 6/6,THUR 6/7)HPA: 9.1,5,13,15; 10.2,3,16,24

SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL): Schottky diodes, Schottky BJTs, STTL inverter, NAND gate, VTC, fan-out, power dissipation, low power LSTTL, SPICE simulation
OTHER TTL GATES: AND gates, NOR gates, OR gates, AOI gates, XOR gates, Schmitt inverters and NAND gates, tri-state buffers(Some answers7.1,7.2,7.4; 8.2,8.3;9.1, 9.2, 9.3; 10.1, 10.2,10.3

LECTURE 8 MID-TERM EXAM I MON (6/11)
Physical Sciences Bldg PS H 153 LECTURE 9 (TUES 6/12) HPA: 11.1,6,8,14,19; 12.1,4,7,10

EMITTER-COUPLED LOGIC (ECL): BJT current switch, VTC, NOR/OR gate, output buffers, MECL I, fan-out, power dissipation, SPICE simulation. TEMPERATURE COMPENSATING ECL: MECL II, bias network, fan-out, power dissipation, SPICE simulation

LECTURE 10 (WEDS 6/13) HPA: 13.1,3,10,14; 14.1,5,8,10

MORE ECL: MECL III, ECL 10K, ECL100K, power dissipation, SPICE simulation

LECTURE 11 (THUR 6/14) HPA: 15.2,3,5,6

OTHER ECL GATES: NOR/OR gates, collector dotting, series gating, NAND/AND gates, complex OR-AND gates, XNOR/XOR gates Schmitt triggers

LECTURE 12(MON 6/18) JUNE 18, MON: MID-TERM EXAM I REVIEW

LECTURE 13 (TUES 6/19) HPA:16.2,6,11,12;17.2,9,13,20;18.1,2,3,10
        MOSFETs:metal gate, silicon gate, N- & P-channel, modes of operation,transconductance
        parameter, threshold voltage, capacitance, SPICE model, CMOS devices, stacked
        MOSFETs
RESISTOR LOADED NMOS INVERTER: operation,graphical determinationof VTC, calculation of critical voltages, power dissipation, SPICE simulation

LECTURE 14,15 (WEDS ,THUR 6/20,21) HPA: 19.1,2,3,17; 20.1,2,3,7; 21.1,2,3,11

SATURATED ENHANCEMENT-ONLY LOADED NMOS INVERTER: same as R-loaded

LINEAR E-O LOADED NMOS INVERTER: same as R-loaded

ENHANCEMENT-DEPLETION LOADED NMOS INVERTER: same as R-loaded

NMOS GATES: NOR, NAND, OR, AND, AOIs, XOR/XNOR, trans gates,
Schmitt inverter

LECTURE 16 (MON 6/25) HPA: 22.2,3,5,9,15,31,38,40,43,50
Review for MID-TERM Exam 2 and see special problems in Chapters 11 through 22(some answers 11.1, 11.3,11.4 ; 12.1,12.2,12.3; 13 .1, 13.2, 13.3; 14.1, 14.2, 14.3;15.1,15.2,15.3; 16.1,16.2, 16.3; 17.1,17.2,17.3; 18-19 1, 2,3, 4, 5 20-21 1,2,3,4 )

MID-TERM EXAM 2 TUES (6/26)
Physical Sciences Bldg PS H 153

LECTURE 17,18 (WED,THUR 6/27,28 ) HPA: 23.1,2,3,4; 24.1,2,3,4,7,12,13,21,31,34,35
CMOS INVERTER: operation, power dissipation, graphical determination of VTC, calculation of critical voltages, design of symmetric inverter or minimum size, inverter capacitance, dynamic response, SPICE simulation, latch-up, input clamping

LECTURE 19,20 (MON,TUES 7/2,3)HPA: 25.1,2,4,7,11; 26.1,3,8,10,13,15; 27.1,3,5,7;28.2,4,8,16,19

CMOS TRI-STATE LOGIC GATES: high impedance Z-states, contention X-states, tri-state inverters, applications, transmission gates
CMOS SCHMITT TRIGGER GATES: inverter, operation and VTC, design, buffered, output, feedback, NAND gate. CMOS DRIVERS: cascaded inverters driving a load cap, multi-stage inverter driver, tri-state pad drivers, break-before-make circuit
DYNAMIC CMOS

WEDS July 4, 2001 INDEPENDENCE DAY

LECTURE 21(THURS,7/5) SPECIAL ASSIGNMENT BiCMOS 30.4,5,9

JULY 9, MON: MID-TERM EXAM 2 REVIEW

LECTURE 22 (TUES 7/10) HPA: 34.3,6,7,10; 35.2,5,7,10

GaAs METAL SEMICONDUCTOR FETs (MESFETs): N-channel, E-D, E-O, modes of operation, transconductance parameter, threshold voltage, capacitance, SPICE simulation
DIRECT COUPLED NMESFET INVERTER (DCFL): E-O inverter, operation, graphical determination of VTC, calculation of critical voltages, power dissipation, fan-out, SPICE simulation

LECTURE 23 (WEDS 7/11) HPA: 36.2,3,4,6; 37.1,2,3,4

SCHOTTKY DIODE NMESFET LOGIC (SDFL) INVERTER: E-D inverters,operation, calculation of critical voltages, power dissipation, fan-out, SPICE simulation.
BUFFERED NMESFET LOGIC (BFL) INVERTER: same as SDFL inverter.

LECTURE 24 (THUR 7/12 ) HPA: 39.1,2,3,9

Review DCFL, SDFL and BFL GaAs digital ICs. GaAs LOGIC FAMILY GATES: DCFL NOR, NAND and OR GATES, SDFL NOR and NAND gates, BFL NOR and NAND gates, complex AOI & OIA gates, DCFL XOR, other OR/NOR gates and GaAs Digital IC Problem Session

LECTURE 25(MON,7/16) ROMs and RAMs Ch 31 and 32 and BJT Digital IC Review for Final Exam

LECTURE 26 ( TUES 7/17) Review NMOS and CMOS and CMOS Problem Session(See problems in Chapters 16 thru 25;some answers: 23.1, 2, 3, 4 and 5; 24. 2, 4, 6, 8, 10; 25.1, 2, 3, 4, 5, 6 and Preparation for MID-TERM EXAM II

MID-TERM EXAM 3 WED (7/18)
(Chapters 23-39,omitting (29 to 33)
Physical Sciences Bldg PS H 153
FINAL EXAM Thursday 7/19
Physical Sciences Bldg PS H 153
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