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   Maintained
by: Aditya
Rastogi ; Updated: February 16, 2002 |
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1. Aggregation and Forecasting of Interrelated Demands for Effective Operation Planning
Argon Chen (National Taiwan University) achen@ccms.ntu.edu.tw
2. Integrating Multi-Level Capacity Planning for Semiconductor Manufacturing
Yon-Chun Chou (National Taiwan University) ychou@ccms.ntu.edu.tw
3. Framework for the Performance Assessment of Shop floor Control Systems
Oliver Rose (University of Wurzburg) rose@informatik.uni-wuerzburg.de
1. Resource-Driven and Job-Driven Simulations
Theresa Roeder (University of California, Berkeley) roeder@ieor.berkeley.edu
2. Demonstrated Benefits of Cluster Tools Simulation
Deborah Pederson (University of California, Berkeley) Debbie@ieor.berkeley.edu
3. Rescheduling Strategies for Complex Job Shops
Scott Mason (University of Arkansas) mason@uark.edu
1. Extremely Hot Lots: Super-Expediting in a 0.18 Micron Wafer Fab
Jennifer Robinson (FabTime) Jennifer.robinson@fabtime.com
2. Adding System Capacity to a Semiconductor Manufacturing Process via X-Factor and
Bottleneck Regulation Deana R. Delp (Arizona State University) deana.delp@asu.edu
3. An Effective Alarm System for Cycle Time Management
David Muh-Cherng Wu (National Chiao Tung University) mcwu@cc.nctu.edu.tw
4. 300 mm Semiconductor Manufacturing Cycle Time Strategies Assessment through a
DOE Based on Dynamic Simulation Dominique Mercier (STMicroelectronics)
1. Introducing Rapid Modeling and Design Environment (RMDE) Concept: Streamlining the Fab Design Process
Igor Paprotny (Dartmouth College) igorpapa@tahoe.cs.dartmouth.edu
2. Extracting the Most Out of Your Simulation Model: A New System for Planning,
Executing, and Feedback Allan Ravitch (STMicroelectronics) allan.ravitch@st.com
3. Applications of Simulation Modeling at a Texas Instruments DM0S5 Wafer Fab
Kishore Potti & Amit Gupta (Texas Instruments) k-potti@ti.com amitgupta@ti.com
4. Modeling and Performance Control of Capacitated Re-entrant Lines
Spyros Reveliotis (Georgia Institute of Technology) spyros@isye.gatech.edu
1. A Customer-Driven Capacity Exchange Mechanism for Semiconductor Foundry
Pao-Long Chang (National Chiao Tung University) paolong@cc.nctu.edu.tw
2. A Cycle Time Based Capacity Planning System
His-Mei Hsu (National Chiao Tung University) hsimei@cc.nctu.edu.tw
3. Semiconductor Tool Planning via Multi-Stage Stochastic Interger Programming
Shabbir Ahmed (Georgia Institute of Technology) sahmed@isye.gatech.edu
1. Factory Level Productivity Metrics: Basis for Improvement
Mousalam Razzak (Intelligent Quality Systems) mrazzak@iqsystemsltd.com
2. A Proposed Semiconductor Industry Standard for Definition and Measurement of Factory Level Productivity
Ron Billings (FABQ) ron.billings@ieee.org
3. A Hierarchical Approach to Cost Analysis for Next Generation Semiconductor Processes
Neal Pierce (Motorola) neal.pierce@motorola.com
1. Using Manufacturing Rules to Implement Daily Production Plans in a Wafer Fabrication
Facility Hung-Nan Chen (Motorla, Inc.) hung-nan.chen@motorola.com
2. Dynamic Capacity Adjustment for IC Foundries
His-Mei Hsu (National Chiao Tung University) hsimei@cc.nctu.edu.tw
3. The Construction of an Order Exchange Mechanism for Wafer Fabs
Shu-Hsing Chung (National Chiao Tung University) t7533@cc.nctu.edu.tw
1. Incorporating Material Handing into Queuing Network Models of Manufacturing Systems
Guy Curry (Texas A&M University) g-curry@tamu.edu
2. DPPS Scheduling Policies in Semiconductor Wafer Fabs
Jim Dai (Georgia Institute of Technology) dai@isye.gatech.edu
3. Heuristic Methods for Near-Optimal Wafer Fab Scheduling and Dispatching using
Multiclass Fluid Networks Ron Billings (FABQ) ron.billings@ieee.org
4. Use of Analytical Queuing Approximation to Set Processing Step Performance Targets at Infineon Technologies
Dresden Wolfgang Scholl (Infineon Technologies)
1. Lot-sizing and Scheduling in Semiconductor Assembly -A Hierarchical Planning Approach
Heinrich Kuhn (Catholic University of Eichstaett-Ingolstadt)
heinrich.kuhn@ku-eichstaett.de
2. Heuristic Algorithm for Minimizing Earliness-Tardiness on a Single Burn-In Oven in
Semiconductor Manufacturing You In Choung (Arizona State Univeristy)
3. Approaches to Multiobjective Scheduling Optimization in Semiconductor Back-End
Amit Kumar Gupta (Nanyang Technological University, Singapore)
1. An Algorithm for Estimating the Performance of an Automated Material Handling
System for the Semiconductor Industry Jay Wesley Steele (PRI Automation)
2. Evaluation and Comparison of a Car-Based vs a CFT Material Handling System for
a 300 mm Fab Frederika Tausch (Asyst Technologies) Larry Hennessey
(Industrial Design Corporation) ftausch@asyst.com larry.hennessy@idc-ch2m.com
3. 3. Comparative Analysis of 300 mm Automated Material Handling Systems (AMHS)
Kristin Rust (International SEMATECH) Kristin.rust@sematech.org
4. Simulation Model Analysis of Intrabay Automation’s AMHS w/Area Elevators for an
8 inch Wafer Fab D’Arcy Collins (ACADZ, Inc.) darcy@acadzinc.com
1. A Taxonomy of Scheduling Problems in Semiconductor Device Test Operations
Tali Freed (Univeristy of Miami, Coral Gables) tfreed@miami.edu
2. Cycle-Time Reduction Under Product Diversity in Semiconductor Back-End Manufacturing
Cheng-Siong Bong (Infineon Technologies) cheng-siong.bong@infineon.com
1. Scheduling Jobs Containing Multiple Order
Scott Mason (University of Arkansas) mason@uark.edu
2. A Genetic Algorithm for Scheduling Parallel Batch Processing Machines
Scott Mason (University of Arkansas) mason@uark.edu
3. A Genetic Algorithm Heuristic Applied to Stepper Scheduling
Lars Monch (Technical University of Ilmenau) lars.moench@tu-ilmenau.de
4. A Two-Stage Algorithm for Parallel Machine Scheduling with Setup Times and
Tooling Constraints Shin-Ming Guo (I-Shou University) smguo@isu.edu.tw