OVERVIEW

Real-time applications for command and control and communications and signal processing require hundreds of teraflops of processing speed as well as terabit memories. The scaling of device feature sizes into nanometer dimensions can conceivably allow systems made with these components to fulfill these requirements although the development of conventional silicon technology is approaching considerable limitations. On the other hand, we are at the point where atomistic control can be utilized to fabricate extremely small nanoelectronic components, if the appropriate architecture can be developed to enhance the local processing requirements. Indeed, this breakthrough in nanolithography allows us to now conceive of extremely small quantum devices, in which phase coherence can be maintained in the transport, which may itself involve only one or a few electrons. However, to have architectures that can provide the potential speed improvements available with scaling to these quantum devices, and to reduce power consumption, new interconnection schemes are needed which are appropriate for such a new technology.

In this program of research, the nature of future quantum scaled devices, their interconnections, and their applicabilities in new cellular architectures are examined. We envision a system based upon the synergy between the cellular architecture paradigm and a new (predominantly Si-based) technology of multiple active layers of nanodevices within a single processing cell. Our approach, represented schematically below, couples standard MOSFET logic gates, with feature sizes of 50 nm or less, to single-electron semiconductor based quantum dot structures, and to sensing elements at the topmost integration level, to implement the mainly locally interconnected cellular architecture.

First, we propose to work on possible extensions of current technology by investigating novel quantum dot fabrication and simulation on a 1-10 nm scale. Secondly, our vision is to couple the quantum dot system to traditional, but ultrasmall MOS based technology. Quantum dot memory, or processing levels, can then be integrated with conventional technology. Third, this program will focus upon fabrication of special local cell circuits. Throughout this research, we propose to combine the technological investigations with modeling and simulation at the appropriate hierarchical level. We will include aspects of modeling and simulation of multilayer nanodevice stacks and nonlinear dynamics of interconnected architectures. Atomic level modeling will be pursued to understand the ultimate limits of lithography, and to engineer on a molecular scale new prototypes for single electron systems. We will also investigate novel architectures within the context of technological boundary conditions.

Last Updated on November 17 2000 by Milorad Felbapov