Publications

    2009

  1. R. Krishnan, M. Debole, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “New-Age: A NBTI-estimation framework for microarchitectural components,” to be published at International  Journal of Parallel Programming.
  2. R. Singal, A. Balijepalli, A. Subramaniam, C.-C. Wang, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of the non-rectangular gate effect for post-lithography circuit simulation,” to be published in IEEE Transactions on VLSI Systems.
  3. W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, Y. Cao, “The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis,” to be published in IEEE Transactions on VLSI Systems.
  4. M. Chen, W. Zhao, F. Liu, Y. Cao, “Finite-point based transistor model: A new approach to fast circuit simulation,” to be published in IEEE Transactions on VLSI Systems.
  5. X. . Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variation-aware supply voltage assignment for minimizing circuit aging and leakage,” to be published in International Symposium on Low Power Electronics and Design, 2009.
  6. C.-C. Wang, W. Zhao, M. Chen, Y. Cao, “Compact modeling of stress effects in scaled CMOS,” to be published at International Conference on Simulation of Semiconductor Processes and Devices, 2009.
  7. Y. Ye, F. Liu, M. Chen, Y. Cao, “Variability analysis under layout pattern-dependent rapid-thermal annealing process,” to be published at Design Automation Conference, 2009.
  8. Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, and H. Yang, “Gate replacement techniques for simultaneous leakage and aging optimization,” to be published at Design, Automation and Test in Europe, 2009.
  9. Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, H. Yang, “On the efficacy of input vector control to mitigate circuit aging and leakage,” to be published at International Symposium on Quality Electronic Design, 2009.
  10. Y. Ye, F. Liu, Y. Cao, “Modeling of threshold voltage shift under pattern-dependent RTA process,” SPIE Design for Manufacturability through Design-Process Integration III, vol. 7275, 72751T-1-9, 2009.
  11. C.-C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao, “Predictive modeling of layout-dependent stress effect in scaled CMOS design,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
  12. J. Ni, M. Chen, X. Lin, Y. Cao, “Adaptive transistor model for fast circuit simulation,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
  13. W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. R. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 1, pp. 196-203, February 2009.
  14. M. Debole, R. Krishnan, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “New-Age: A framework for NBTI estimation,” Asia and South Pacific Design Automation Conference, pp. 455-460, 2009.

    15. 2008

  15. J. M. Wang, Y. Cao, M. Chen, J. Sun, A. Mitev, and K. Potluri, “Capturing device mismatch in analog and mixed-signal designs,” IEEE Circuits and Systems Magazine., vol. 8, no. 4, pp. 37-44, 2008. [invited]
  16. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “A scalable model for predicting the effect of NBTI for reliable design,” IET Circuits, Devices & Systems., vol. 2, no. 4, pp. 361-371, 2008.
  17. T. Austin, V. Bertacco, S. Mahlke, Y. Cao, “Reliable systems on unreliable fabrics,” IEEE Design & Test of Computers, vol. 25, no. 4, pp. 322-332, February 2008. [invited]
  18. W. Wang, V. Balakrishnan, B. Yang, Y. Cao, “Statistical prediction of NBTI-induced circuit aging,” International Conference on Solid-State and Integrated-Circuit Technology, pp. 416-419, 2008. [invited]
  19. M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, B. C. Paul, Y. Cao, S. Mitra, “Optimized circuit failure prediction for aging: practicality and promise,” International Test Conference, no. 26.1, 2008.
  20. W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Custom Integrated Circuits Conference, pp. 13-16, 2008.
  21. C.-C. Wang, W. Zhao, Y. Cao, “Predictive modeling of layout-dependent carrier mobility in stressed CMOS technology,” SRC TECHNON, 2008.
  22. V. Balakrishnan, W. Wang, Y. Cao, “Statistical prediction of circuit aging under process and design uncertainties,” SRC TECHNON, 2008.
  23. Y. Ye, F. Liu, S. Nassif, Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,” Design Automation Conference, pp. 900-905, 2008.
  24. S. Sinha, A. Balijepalli, Y. Cao, “A simplified model of carbon nanotube transistor with applications to analog and digital design,” International Symposium on Quality Electronic Design, pp. 502-507, 2008.
  25. W. Wang, S. Yang, and Y. Cao, “Node criticality computation for circuit timing analysis and optimization under NBTI effect,” International Symposium on Quality Electronic Design, pp. 763-768, 2008.
  26. X. Li, Y. Cao, “Projection-based piecewise-linear response surface modeling for strongly nonlinear VLSI performance variations,” International Symposium on Quality Electronic Design, pp. 108-113, 2008.
  27. D. Ganesan, A. Mitev, J. Wang, Y. Cao, “Finite-point gate model for fast timing and power analysis,” International Symposium on Quality Electronic Design, pp. 657-662, 2008.
  28. L. Cheng, Y. Lin, L. He, and Y. Cao, “Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability,” International Symposium on Field-Programmable Gate Arrays, pp. 159-168, 2008.
  29. M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, Y. Cao, S. Mitra, "Optimized circuit fialure prediction for aging: practicality and promise," International Workshop on Timing Issues in teh Spcification and Synthesis of Digital System (TAU), 2008.
  30. B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343-365, February 2008. [invited]
  31. A. Subramaniam, R. Singhal, C.-C. Wang, Y. Cao, “Design rule optimization of regular layout for leakage reduction in nanoscale design,” Asia and South Pacific Design Automation Conference, pp. 474-479, 2008.

    32. 2007

  32. W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit reliability for 65nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, pp. 509-517, December 2007. [invited]
  33. Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1866-1873, October 2007.
  34. W. Zhao and Y. Cao, “Predictive technology model for nano-CMOS design exploration,” ACM Journal on Emerging Technologies in Computing Systems, vol. 3, no. 1, pp. 1-17, April 2007.
  35. W. Zhao, X. Li, M. Nowak, and Y. Cao, "Predictive technology modeling for 32nm low power design," to be published at International Semiconductor Device Research Symposium, 2007.
  36. W. Wang, Z. Wei, S. Yang, Y. Cao, “An efficient method to identify critical gates under circuit aging,” International Conference on Computer Aided Design, pp. 735-740, 2007.
  37. D. Ganesan, D. Shanmugasundaram, A. Mitev, Y. Cao, J. Wang, “A robust finite-point based gate model considering process variations,” International Conference on Computer Aided Design, pp. 692-697, 2007.
  38. Y. Cao, C. C. McAndrew, “MOSFET modeling for 45nm and beyond,” embedded tutorial, International Conference on Computer Aided Design, pp. 638-643, 2007. [invited]
  39. W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” Custom Integrated Circuits Conference, pp. 511-514, 2007.
  40. W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” European Solid-State Circuits Conference, pp. 89-92, 2007.
  41. W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” SRC TECHNON, 2007.
  42. A. Balijepalli, S. Sinha, Y. Cao, “Compact modeling of carbon nanotube transistor for early stage process-design exploration,” International Symposium on Low Power Electronics and Design, pp. 2-7, 2007. [best paper award]
  43. W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Design Automation Conference, pp. 364-369, 2007. [PDF]
  44. R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of non-rectangular gate for post-lithography circuit simulation,” Design Automation Conference, pp. 823-828, 2007.
  45. M. Chen, W. Zhao, F. Liu, Y. Cao, “Fast statistical circuit analysis with finite-point based transistor model,” Design, Automation and Test in Europe, pp. 1391-1396, 2007.
  46. A. Balijepalli, J. Ervin, Y. Cao, and T. Thornton, “Compact modeling of a PD SOI MESFET for wide-temperature designs,” International Symposium on Quality Electronic Design, pp. 133-138, 2007.
  47. R. Vattikonda, Y. Luo, A. Gyure, X. Qi, S. Lo, M. Shahram, Y. Cao, K. Singhal, and D. Toffolon, “A new simulation method for NBTI analysis in SPICE environment,” International Symposium on Quality Electronic Design, pp. 41-46, 2007.
  48. T. Sairam, W. Zhao, Y. Cao, “Optimizing FinFET technology for high-speed and low-power design,” Great Lakes Symposium on VLSI, pp. 73-77, 2007. [best paper award nominee]

    49. 2006

  49. H. Qin, R. Vattikonda, T. Trinh, Y. Cao, J. Rabaey, “SRAM cell optimization for ultra-low power standby,” ASP Journal of Low Power Electronics, vol. 2, no. 3, pp. 401-411, December 2006.
  50. W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
  51. J. He, M. Fang, B. Li, G. Zhang, Y. Cao, “A new analytic approximation to general diode equation,” Elsevier Solid-State Electronics, vol. 50, no. 9, pp. 1371-1374, September 2006.
  52. S. Bhardwaj, Y. Cao, S. Vrudhula, “Statistical leakage minimization of digital circuits using gate sizing, gate length biasing, and threshold voltage selection,” ASP Journal of Low Power Electronics, vol. 2, no. 2, pp. 240-250, August 2006.
  53. B. T. Cline, K. Chopra, D. Blaauw, and Y. Cao “Analysis and modeling of CD variation for statistical static timing,” International Conference on Computer Aided Design, pp. 60-66, 2006.
  54. Y. Cao, W. Zhao, “Predictive technology model for nano-CMOS design exploration,” International Conference on Nano-Networks, 2006. [invited]
  55. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “Predictive modeling of the NBTI effect for reliable design,” Custom Integrated Circuits Conference, pp. 189-192, 2006.
  56. R. Vattikonda, W. Wang, Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” Design Automation Conference, pp. 1047-1052, 2006.
  57. S. Bhardwaj, S. Vrudhula, Praveen Ghanta, Y. Cao, “Modeling of intra-die process variations for accurate analysis and optimization of nanoscale circuits,” Design Automation Conference, pp. 791-796, 2006.
  58. A. Balijepalli, J. Ervin, P. Joshi, J. Yang, Y. Cao, and T. J. Thornton, “High-voltage CMOS compatible SOI MESFET characterization and SPICE model extraction,” IEEE International Microwave Symposium, pp. 1335-1338, 2006.
  59. S. Bhardwaj, S. Vrudhula, and Y. Cao, “LOTUS: leakage optimization under timing uncertainty for standard-cell designs,” International Symposium on Quality electronic Design, pp. 717-722, 2006.
  60. W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45nm design exploration,” International Symposium on Quality Electronic Design, pp. 585-590, 2006. [best paper award nominee]
  61. M. Chen and Y. Cao, “Analysis of pulse signaling for low-power on-chip global bus design,” International Symposium on Quality electronic Design, pp. 401-406, 2006.
  62. S. Bhardwaj, Y. Cao, and S. Vrudhula, “Statistical leakage minimization using gate sizing, gate length biasing and threshold voltage selection,” Asia and South Pacific Design Automation Conference, pp. 953-958, 2006. [best paper award nominee]

    63. 2005

  63. J. Chen, L. T. Clark, and Y. Cao, “Maximum Fan-In/Out: Ultra-low voltage circuit design in the presence of variations,” IEEE Circuits and Devices Magazine, vol. 21, no. 6, pp. 12-20, November 2005.
  64. Y. Cao, X.-D. Yang, X. Huang, and D. Sylvester, "Switch-factor based loop RLC modeling for efficient timing analysis," IEEE Transactions on VLSI Systems, vol. 13, no. 9, pp. 1072-1078, September 2005.
  65. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. M. Rabaey, "Standby supply voltage minimization for deep sub-micron SRAM," Elsevier Microelectronics Journal, vol. 36, no. 9, pp. 789-800, September 2005.
  66. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," IEEE Transactions on VLSI Systems, vol. 13, no. 1, pp. 158-162, January 2005.
  67. J. Chen, L. T. Clark, Y. Cao, “Robust subthreshold design of high fan-in/out circuits,” International Conference on Computer Design, pp. 405-410, 2005.
  68. Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” Design Automation Conference, pp. 658-663, 2005.
  69. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling within-die spatial correlation effects for process-design co-optimization,” Microlithography Program, SPIE, 2005.
  70. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling within-die spatial correlation effects for process-design co-optimization,” International Symposium on Quality Electronic Design, pp. 516-521, 2005.
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